View FAN6520A06_717821.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FAN6520A Single Synchronous Buck PWM Controller
October 2006
FAN6520A Single Synchronous Buck PWM Controller
Features
Output Range: 0.8V to VIN
Description
The FAN6520A simplifies implementing a complete control and protection scheme for a DC-DC stepdown converter. Designed to drive N-channel MOSFETs in a synchro-nous buck topology, the FAN6520A integrates the control, output adjustment, monitoring, and protection functions into a single 8-lead package. The FAN6520A employs a single feedback loop and voltage-mode control with fast transient response. The output voltage can be precisely regulated to as low as 0.8V, with a maximum tolerance of 1.5% over-temperature and line-voltage variations. A fixed-frequency oscillator reduces design complexity, while balancing typical application cost. The error amplifier features a 15MHz gainbandwidth product and an 8V/s slew rate, which enables high converter bandwidth for fast transient performance. The resulting PWM duty cycles range from 0% to 100%. The IC monitors the drop across the upper MOSFET and inhibits PWM operation appropriately to protect against over-current conditions. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor. The FAN6520A is rated for operation from 0 to +70C, with the FAN6520AI rated from -40 to +85C.

- 0.8V Internal Reference - 1.5% Over Line Voltage and Temperature Drives N-Channel MOSFETs Simple Single-Loop Control Design - Voltage-Mode PWM Control Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Cycle Lossless, Programmable, Over-Current Protection - Uses Upper MOSFET's RDS(ON) Small Converter Size - 300kHz Fixed-Frequency Oscillator - Internal Soft-Start - 8-Lead SOIC
Applications
Power Supplies for PC Subsystems and Peripherals MCH, GTL, and AGP Supplies Cable Modems, Set-Top Boxes, and DSL Modems DSP, Memory Low-Voltage Distributed Power Supplies
Ordering Information
Part Number
FAN6520AM FAN6520AMX FAN6520AIM FAN6520AIMX
Temperature Range
0C to 70C 0C to 70C -40C to 85C -40C to 85C
Package
SOIC-8 SOIC-8 SOIC-8 SOIC-8
Packing
Rails Tape and Reel Rails Tape and Reel
(c) 2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com
FAN6520A Single Synchronous Buck PWM Controller
Pin Configuration
BOOT HDRV GND LDRV
1 2 3 4 FAN6520A
8 7 6 5
SW COMP/OCSET/SD FB VCC
FAN6520AM 8-Pin SOIC Package
Pin Definitions
Pin #
1 2
Name
BOOT HDRV
Description
Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver. Connect to bootstrap capacitor, as shown in Figure 1. High-Side Gate-Drive Output. Connect to the gate of the high-side power MOSFET(s). This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. Ground. The signal and power ground for the IC. Tie this pin to the ground island/plane through the lowest impedance connection available. Connect directly to source of low-side MOSFET(s). Low-Side Gate-Drive Output. Connect to the gate of the low-side power MOSFET(s). This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic capacitor as close to this pin as possible. Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP/OCSET pin, to compensate the voltage-control feedback loop of the converter. Compensation / Over-Current Set Point / Shut Down. This is a multiplexed pin. During operation, the output of the error amplifier drives this pin. During a short period of time following power-on reset (POR), this pin is used to determine the over-current threshold of the converter. Pulling COMP/OCSET to a level below 0.8V disables the controller. Disabling the controller causes the oscillator to stop, the HDRV and LDRV outputs to be held low, and the soft-start circuitry to restart. Switch Node Input. The SW pin provides return for the high-side bootstrapped driver, is a sense point for the adaptive shoot-through protection, and is used to monitor the drop across the upper MOSFET's RDS(ON) for current limit. Connect as shown in Figure 1.
3
GND
4
LDRV
5 6
VCC FB
7
COMP/ OCSET/SD
8
SW
(c) 2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 2
FAN6520A Single Synchronous Buck PWM Controller
Typical Application
+5V D BOOT 1 VCC C VCC BOOT C BOOT C BULK Q1 2 HDRV SW Q2 LDRV GND FB RS R OFFSET LOUT +VOUT C OUT C HF
5
R OCSET
FAN6520A
8
4 3 COMP/OCSET 7 6
RF
CF CI
Figure 1. Typical Application
VCC
POR / SOFT-START
INHIBIT
BOOT HDRV SW
SAMPLE & HOLD
OC
COMP/OCSET FB 20A ERROR AMP 0.8V
PWM
PWM
GATE CONTROL LOGIC
VCC LDRV GND
OSC
Figure 2. Functional Block Diagram
(c) 2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 3
FAN6520A Single Synchronous Buck PWM Controller
Absolute Maximum Ratings
The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table defines the conditions for actual device operation.
Parameter
VCC to GND VBOOT to GND HDRV (VBOOT - VSW) LDRV SW to PGND All other pins Continuous Transient ( t < 50ns, F < 500kHz)
Min.
Max.
6 15 6
Units
V V V V V V V
-0.5 -0.5 -3
6 6 7 5.5
Thermal Information
Symbol
TSTG TL
Parameter
Storage Temperature Lead Soldering Temperature, 10 seconds Vapor Phase, 60 seconds Infrared, 15 seconds
Min.
-65
Typ.
Max.
150 300 215 220 715
Units
C C C C mW C/W C/W
PD JC JA
Power Dissipation, TA = 25C Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient 40 140
Recommended Operating Conditions
Symbol
VCC TA TJ
Parameter
Supply Voltage Ambient Temperature Junction Temperature
Conditions
VCC to PGND FAN6520A FAN6520AI
Min.
4.5 0 -40 -40
Typ.
5
Max.
5.5 70 85 125
Units
V C C C
(c) 2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 4
FAN6520A Single Synchronous Buck PWM Controller
Electrical Specifications
VCC = 5V and TA = 25C, using the circuit shown in Figure 1 unless otherwise noted. The * denotes specifications that apply over the full operating temperature range.
Symbol Parameter
Supply Current IVCC POR Oscillator FOSC VOSC Reference VREF Reference Voltage Frequency Ramp Amplitude VCC Current Rising VCC POR Threshold VCC POR Threshold Hysteresis
Conditions
HDRV, LDRV open * *
Min.
1.5 4.00
Typ.
2.4 4.22 170
Max.
3.8 4.45
Units
mA V mV
Power-On Reset
FAN6520A FAN6520AI
* * *
250 230
300 300 1.5
340 340
kHz kHz Vp-p
TA = 0 to 70C FAN6520AI
* *
788 780
800 800 88 15 8 2.5 2.0 2.5 1.0
812 820
mV mV dB MHz V/s
Error Amplifier DC Gain GBWP S/R RHUP RHDN RLUP RLDN IOCSET Gain - Bandwidth Product Slew Rate HDRV Pulll-Up Resistance HDRV Pull-Down Resistance LDRV Pull-Up Resistance LDRV Pull-Down Resistance OCSET Current Source FAN6520A FAN6520AI VDISABLE Disable Threshold * * 17 14
Gate Drivers
Protection/Disable 20 20 800 22 24 A A mV
Notes: 1. All limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control. 2. AC specifications guaranteed by design/characterization (not production tested).
(c) 2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 5
FAN6520A Single Synchronous Buck PWM Controller
Circuit Description
Initialization
The FAN6520A automatically initializes upon receipt of power. The Power-On Reset (POR) function continually monitors the bias voltage at the VCC pin. When the supply voltage exceeds its POR threshold, the IC initiates the Over-Current Protection (OCP) sample-and-hold operation. Upon completion of the OCP sample-and-hold operation, the POR function initiates soft-start operation. The over-current function trips at a peak inductor current (IPEAK) determined by: I OCSET x R OCSET I PEAK = ----------------------------------------------R DS ( ON ) (1)
Over-Current Protection
The over-current function protects the converter from a shorted output by using the upper MOSFET's on-resistance, RDS(ON), to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating the need for a current-sensing resistor. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level (see Typical Application diagram). Immediately following POR, the FAN6520A initiates the Over-Current Protection sampling-and-hold operation. First, the internal error amplifier is disabled. This allows an internal 20A current sink to develop a voltage across ROCSET. The FAN6520A then samples this voltage at the COMP pin. This sampled voltage, which is referenced to the VCC pin, is held internally as the over-current set point. When the voltage across the upper MOSFET, which is also referenced to the VCC pin, exceeds the over-current set point, the over-current function initiates a soft-start sequence. Figure 3 shows the inductor current after a fault is introduced while running at 15A. The continuous fault causes the FAN6520A to go into a hiccup mode with a typical period of 25ms. The inductor current increases to 18A during the soft-start interval and causes an over-current trip. The converter dissipates very little power with this method. The measured input power for the conditions shown in Figure 3 is 1.5W.
where IOCSET is the internal OCSET current source (20A typical). The OC trip point varies mainly due to the MOSFET's RDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: * The maximum RDS(ON) at the highest junction temperature * The minimum IOCSET from the specification table I * Determine IPEAK for I PEAK > I OUT ( MAX ) + ---2 where I is the output inductor ripple current. For an equation for the ripple current, see "Output Inductor (Lout)" under Component Selection. Internal circuitry of the FAN6520A does not recognize a voltage drop across ROCSET larger than 0.5V. Any voltage drop across ROCSET greater than 0.5V sets the overcurrent trip point to: 0.5V I PEAK = ---------------------(2) R
DS ( ON )
An over-current trip cycles the soft-start function.
Soft-Start
The POR function initiates the soft-start sequence after the over-current set point has been sampled. Soft-start clamps the error amplifier output (COMP pin) and reference input (noninverting terminal of the error amp) to the internally generated soft-start voltage. Figure 4 shows a typical start-up interval where the COMP/OCSET pin has been released from a grounded (system shutdown) state. Initially, the COMP/OCSET is used to sample the over-current set point by disabling the error amplifier and drawing 20A through ROCSET. Once the over-current level has been sampled, the soft-start function is initiated. The clamp on the error amplifier (COMP/OCSET pin) initially controls the converter's output voltage during soft-start. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates SW pulses of increasing width that charge the output capacitor(s). When the internally generated softstart voltage exceeds the feedback (FB pin) voltage, the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The entire startup sequence typically takes about 11ms.
OUTPUT INDUCTOR CURRENT 5A/DIV.
Figure 3. Over-Current Operation
(c)2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 6
FAN6520A Single Synchronous Buck PWM Controller
Vin Q1 HDRV SW Q2 LDRV L OUT CIN +VOUT COUT
Figure 4. Soft-Start Interval The FAN6520A incorporates a MOSFET shoot-through protection method that allows a converter to both sink and source current. Care should be exercised when designing a converter with the FAN6520A when it is known that the converter may sink current. When the converter is sinking current, it is behaving as a boost converter regulating its input voltage. This means that the converter is boosting current into the VCC rail, which supplies the bias voltage to the FAN6520A. If this current has nowhere to go--such as to other distributed loads on the VCC rail, through a voltage limiting protection device, or other methods--the capacitance on the VCC bus absorbs the current. This allows the voltage level of the VCC rail to increase. If the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of the FAN6520A, the IC experiences an irreversible failure and the converter is no longer operational. Ensure that there is a path for the current to follow, other than the capacitance on the rail, to prevent this failure mode.
Figure 5. Printed Circuit Board Power and Ground Planes or Islands Figure 5 shows the critical power components of the converter. To minimize voltage overshoot, the interconnecting wires (indicated by heavy lines) should be part of a ground or power plane in a printed circuit board. The components shown in Figure 5 should be located as close together as possible. Note that the capacitors CIN and COUT may each represent numerous physical capacitors. Locate the FAN6520A within two inches of the Q1 and Q2 MOSFETs. The circuit traces for the MOSFETs' gate and source connections from the FAN6520A must be sized to handle up to 1A peak current. Figure 5 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the COMP/OCSET pin and locate the resistor, ROSCET, close to the COMP/OCSET pin because the internal current source is only 20A. Provide local VCC decoupling between the VCC and GND pins. Locate the capacitor, CBOOT, as close as practical to the BOOT and PHASE pins. All components used for feedback compensation should be located as close to the IC as practical.
Vin
LOAD
Application Information
Layout Considerations
In any high-frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. Use wide, short-printed traces to minimize interconnecting impedances. The critical components should be located as close together as possible, using ground plane construction or single-point grounding.
BOOT SW +5V CBOOT
Q1 LOUT COUT Q2 +VOUT
LOAD
FAN6520A
ROCSET
DBOOT VCC
+5V CVCC
COMP/OCSET GND
Figure 6. PCB Small Signal Layout Guidelines
(c)2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 7
FAN6520A Single Synchronous Buck PWM Controller
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the SW node. The PWM wave is smoothed by the output LC filter (LOUT and COUT).
VIN OSC L OUT
SW PWM
The compensation network consists of the error amplifier (internal to the FAN6520A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed-loop transfer function with the highest 0dB crossing frequency (F0dB) and adequate phase margin. Phase margin is the difference between the closedloop phase at F0dB and 180 degrees. The equations below relate the compensation network's poles, zeros, and gain to the components (R1, R2, R3, C1, C2, and C3), shown in Figure 7. 1 F Z1 = --------------------2R 2 C 1 1 F P1 = ---------------------------------------C1 C2 2R 2 -------------------- C 1 + C 2 1 F Z2 = --------------------------------------2C 3 ( R 1 + R 3 ) (5)
+VOUT
+5V ZFB COMP
ERROR AMP
ESR
Q2
COUT
(6)
(7) (8)
FB
ZIN
0.8V
1 F P2 = --------------------2R 3 C 3
Use the following steps to locate the poles and zeros of the compensation network: 1. 2.
VOUT
DETAILED COMPENSATION COMPONENTS
Pick gain (R2/R1) for the desired converter bandwidth. Place the first zero below the filter's double pole (~75% FLC). Place the second zero at filter's double pole. Place the first pole at the ESR zero. Place the second pole at half the switching frequency. Check the gain against the error amplifier's openloop gain. Estimate phase margin. Repeat if necessary.
ZFB
C1 R2
C2 C3
ZIN
R3 R1
3. 4. 5.
COMP
ERROR AMP
FB
0.8V
6. 7.
Figure 7. Voltage Mode Buck Converter Compensation Design The modulator transfer function is the small-signal transfer function of VOUT/VCOMP. This function is dominated by a DC gain and the output filter (LOUT and COUT), with a double-pole break frequency at FLC and a zero at FESR. The DC gain of the modulator is the input voltage (VIN) divided by the peak-to-peak oscillator voltage (VOSC. ) The following equations define the modulator break frequencies as a function of the output LC filter: 1 F LC = -----------------------2 L x C 1 F ESR = -----------------------------------2 x ESR x C (3)
Figure 8 shows an asymptotic plot of the DC-DC converter's gain vs. frequency. The actual modulator gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 8. Using the above guidelines should give a compensation gain similar to the curve plotted. The open-loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The closed-loop gain is constructed on the graph of Figure 8 by adding the modulator gain (in dB) to the compensation gain (in dB). This is equivalent to multiplying the modulator transfer function by the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable high bandwidth overall loop. A stable control loop has a gain crossing with a -20dB/decade slope and a phase margin greater than 45. Include worst-case component variations when determining phase margin.
(4)
(c)2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 8
FAN6520A Single Synchronous Buck PWM Controller
Output Inductor (LOUT)
100 80 60
GAIN (dB)
FZ1 FZ2
FP1
FP2
OPEN LOOP ERROR AMP GAIN 20LOG (R2/R1) MODULATOR GAIN
40 20 0 -20 -40 FLC -60 10 100 1K 10K FESR 100K 1M 10M 20LOG (VIN/DVOSC) COMPENSATION GAIN CLOSED LOOP GAIN
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage (V) and current (I) are approximated by the following equations: V IN - V OUT V OUT I = ----------------------------- x -------------V IN F SW x L V ESR x I (9)
FREQUENCY (Hz)
Figure 8. Asymptotic Bode Plot of Converter Gain An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout.
Component Selection
Output Capacitors (COUT)
Modern components and loads are capable of producing transient load rates above 1A/ns. High-frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. Effective Series Resistance (ESR) and voltage rating are typically the prime considerations for the bulk filter capacitors, rather than actual capacitance requirements. High-frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the performance of these low-inductance components. Consult with the load manufacturer on specific decoupling requirements. Use only specialized lowESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR determines the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes; however, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Since ESL is not a specified parameter, work with the capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. Generally, multiple small-case electrolytic capacitors perform better than a single large-case capacitor.
Increasing the inductance value reduces the ripple current and voltage, but also reduces the converter's ability to quickly respond to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control-loop design, the FAN6520A provides either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. Depending on whether there is a load application or a load removal, the response time to a load transient (ISTEP) is different. The following equations give the approximate response time interval for application and removal of a transient load: L x I STEP T RISE = ----------------------------V IN - V OUT L x I STEP T FALL = -----------------------V OUT (10)
(11)
where TRISE is the response time to the application of a positive ISTEP and TFALL is the response time to a load removal (negative ISTEP). The worst-case response time can be either at application or removal of load. Check both of these equations at the minimum and maximum output levels for the worst-case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high-frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and the largest RMS current required by the circuit. The capacitor voltage rating should be at least
(c)2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 9
FAN6520A Single Synchronous Buck PWM Controller
1.25 times greater than the maximum input voltage. A voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement (IRMS) for the input capacitor of a buck regulator is: I RMS = I L ( D - D )
2
As described in the equations above, the total power consumed in driving the gate is divided in proportion to the resistances in series with the MOSFET's internal gate node, as shown in Figure 9.
BOOT
(12)
RHUP
HDRV RE
G
Q1
RG
V OUT where the converter duty cycle is D = -------------- . V IN For a through-hole design, several electrolytic capacitors may be needed. For surface-mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor's surge current rating. The capacitors must be capable of handling the surge current at power-up. Some capacitor series available from reputable manufacturers are surge current tested.
RHDN
SW
S
Figure 9. Driver Dissipation Model RG is the polysilicon gate resistance internal to the FET. RE is the external gate drive resistor implemented in many designs. Note that the introduction of RE can reduce driver power dissipation, but excess RE may cause errors in the "adaptive gate drive" circuitry. For more information, please refer to Application Note AN6003, "Shoot-through" in Synchronous Buck Converters at http://www.fairchildsemi.com/an/AN/AN-6006.pdf. PLDRV is dissipation of the lower FET driver. PLDRV = PL(R) x PL(F) (20) where PH(R) and PH(F) are internal dissipations for the rising and falling edges, respectively: R LUP P L ( R ) = P Q2 x -----------------------------------------R LUP + R E + R G R LDN P L ( F ) = P Q2 x ------------------------------------------R HDN + R E + R G where: (21)
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBOOT) and the internal diode, as shown in Figure 1. Select these components after the high-side MOSFET has been chosen. The required capacitance is determined using the following equation: QG C BOOT = ------------------------(13) V BOOT where QG is the total gate charge of the high-side MOSFET and VBOOT is the voltage droop allowed on the high-side MOSFET drive. To prevent loss of gate drive, the bootstrap capacitance should be at least 50 times greater than the CISS of Q1.
Thermal Considerations
Total device dissipation: PD = PQ + PHDRV + PLDRV where PQ represents quiescent power dissipation. PQ = VCC x [4mA + 0.036 (FSW - 100)] where FSW is switching frequency (in kHz). PHDRV represents internal power dissipation of the upper FET driver. PHDRV = PH(R) x PH(F) (16) (15) (14)
(22)
PQ2 = QG2 x VGS(Q2) x FSW.
(23)
Power MOSFET Selection
For more information on MOSFET selection for synchronous buck regulators, refer to: AN-6005: Synchronous Buck MOSFET Loss Calculations at http://www.fairchildsemi.com/an/AN/AN-6005.pdf. Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. In typical applications, the FAN6520A converter's output voltage is low with respect to its input voltage; therefore the lower MOSFET (Q2) is conducting the full load current for most of the cycle. Choose a MOSFET for Q2 that has low RDS(ON) to minimize conduction losses. In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle and its conduction loss has less impact. Q1, however, sees most of the switching losses, so Q1's primary selection criteria should be gate charge.
where PH(R) and PH(F) are internal dissipations for the rising and falling edges respectively. R HUP P H ( R ) = P Q1 x ------------------------------------------R HUP + R E + R G R HDN P H ( F ) = P Q1 x ------------------------------------------R HDN + R E + R G where: PQ1 = QG1 x VGS(Q1) x FSW (19) (17)
(18)
where QG1 is total gate charge of Q1 for its applied VGS.
(c)2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 10
FAN6520A Single Synchronous Buck PWM Controller
High-Side Losses
Figure 10 shows a MOSFET's switching interval, with the upper graph being the voltage and current on the drainto-source and the lower graph detailing VGS vs. time with a constant current charging the gate. The x-axis, therefore, is also representative of gate charge (QG). CISS = CGD + CGS and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from the MOSFET's datasheet. Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses occur during the shaded time when the MOSFET has voltage across it and current through it. These losses are given by: PUPPER = PSW + PCOND V DS x I L P SW = ----------------------- x 2 x t s F SW 2 V OUT 2 P COND = ---------------- x I OUT x R DS ( ON ) V IN (24) (25) (26)
C ISS VDS
C GD
C ISS
ID
QGS QGD
4.5V
V SP V TH
VGS
t1 t2
QG(SW)
t3 t4 t5
Figure 10. Switching Losses and QG
5V CGD RD HDRV G RGATE CGS SW VIN
where PUPPER is the upper MOSFET's total losses, PSW and PCOND are the switching and conduction losses for a given MOSFET, RDS(ON) is at the maximum junction temperature (TJ), and tS is the switching period (rise or fall time) and is t2+t3 (Figure 10). The driver's impedance and CISS determine t2, while t3's period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP, use a constant current assumption for the driver to simplify the calculation of tS:
Figure 11. Drive Equivalent Circuit Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as QG(SW) = QGD + QGS - QTH where QTH is the gate charge required to reach the MOSFET threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should be taken to include the delivery of the MOSFET's gate power (PGATE) in calculating the power dissipation required: PGATE = QG x VCC x FSW where QG is the total gate charge to reach VCC. (28)
Q G ( SW ) Q G ( SW ) t s ------------------------- -------------------------------------------------------------I DRIVER V CC - V SP -------------------------------------------------------- R DRIVER + R GATE
(27)
(c)2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 11
FAN6520A Single Synchronous Buck PWM Controller
Low-Side Losses
Q2, however, switches on or off with its parallel Shottky diode conducting, therefore VDS Y 0.5V. Since PSW is proportional to VDS, Q2's switching losses are negligible and Q2 can be selected based on RDS(ON) only. Conduction losses for Q2 are given by: PCOND = (1-D) x IOUT2 x RDS(ON) (29)
side MOSFET, the J-A, and the maximum allowable ambient temperature rise: T J ( MAX ) - T A ( MAX ) P D ( MAX ) = --------------------------------------------------------J - A (30)
where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and Since DMIN < 20% for portable computers, (1-D) 1 produces a conservative result, simplifying the calculation. The maximum power dissipation (PD(MAX) ) is a function of the maximum allowable die temperature of the lowV OUT D = ----------------- is the minimum duty cycle for the converter. V IN
depends primarily on the amount of PCB area that can be devoted to heat sinking. Refer to Fairchild Application Note AN-1029 Maximum Power Enhancement Techniques for SO-8 Power MOSFETs at http://www.fairchildsemi.com/an/AN/AN-1029.pdf .
(c)2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 12
FAN6520A Single Synchronous Buck PWM Controller
Typical Application Circuit
+5V D1 1 VCC C4 BOOT C6 C13 C12
5 2 HDRV SW
Q1
C5a
C5b
R5
U1 FAN6520A
L OUT Q2 C9-10 R6
R1 C3 R3 C7 R4 R7
8
+VOUT C11
4 3 COMP/OCSET 7 6 SW1
R2 C1 C2
LDRV GND FB
Figure 12. 5V to 1.5V 15A DC-DC Converter
Evaluation Board Bill of Materials (1.5V, 15 Amps):
Ref Des
C1 C2 C3 C4 C5A,C5B C6,C11 C7 C9-10,C12,C13 D1 L1 Q1,Q2 R1 R2 R3 R4 R5 R6 R7 PB1 U1 TP1,2,3,4
Description
100pF Capacitor, 603 0.01F Capacitor, 603 Not Populated 0.1F Capacitor, 603 1F Capacitor, 805 0.1F Capacitor, 603 Not Populated Capacitor, 603 1500F Capacitor, 6.3V Diode, 30mA, 30V 1.2H Inductor MOSFET 2.2k 1% Resistor, 603 30.1k 1% Resistor, 603 Not Populated 2.49k Resistor, 603 11.8k Resistor, 603 Not Populated Resistor, 603 0 Resistor, 603 Pushbutton, miniature Single Synchronous Buck PWM Test Points
Manufacturer
Any Any Any Any Any Any United Chemi-con Fairchild InterTechnical Fairchild Any Any Any Any Any Any Digikey Fairchild KeyStone
P/N
Qty
1 1 0 1 3 2 0
KZJ6.3VB152M10X12LL MMSD4148 SC5015-1R2M FDD6606
4 1 1 2 1 1 0 1 1 0 1
P8007S-ND FAN6520A 1514-2
1 1 4
(c) 2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 13
FAN6520A Single Synchronous Buck PWM Controller
Dimensional Outline Drawing
Figure 13. 8-Lead SOIC Package Drawing
(c) 2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 14
FAN6520A Single Synchronous Buck PWM Controller
(c) 2005 Fairchild Semiconductor Corporation FAN6520A Rev. 1.0.5
www.fairchildsemi.com 15

▲Up To Search▲

Price & Availability of FAN6520A06

	To Download FAN6520A06 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .